Andre Hedrick wrote:
> > for chipsets does not get called. I'll speak specifically about the CSB5.
> > The CSB5 in non-native mode has a PCI irqline register forced to 0. The
> > PCI probe then skips it's PCI init and it never gets called.
OK! This is what I have learned. The ide-pci init code has one case that
isn't caught. Perhaps you can clarify what it means, for me.
* If an IDE controller has a PCI IRQ and has class code bit 0x5 set, it is
100% native.
* CSB5 _CAN_NOT_ have a PCI IRQ assigned (RO register).
* CSB5 spec clearly indicates that you can turn on class code bits 0x5 for
native mode operation.
* My system has the native mode bits turned on, but not an IRQ. The driver
incorrectly drops this case into teh "bad irq" case.
* Solution: cleanup probe to something like:
if ((is_storage_ide || is_storage_other) && native_bits && pciirq) {
/* 100% native mode */
init_chipset();
} else if ((is_storage_ide || is_storage_other) && native_bits) {
/* native mode */
init_chipset();
} else if (is_storage_ide || is_storage_other) {
/* non-native mode */
init_chipset();
} else {
/* what here ?!?! */
}
or simpler:
if (is_storage_ide || is_storage_other) {
if (native_bits && pciirq) {
/* 100% native mode */
} else if (native_bits) {
/* plain-old native mode */
} else {
/* non-native mode */
}
init_chipset();
} else {
/* what here?!? */
}
What do you think of this case? The other alternative is to turn OFF
native bits on any CSB5, since it can't have a PCI IRQ assigned.
Please let me know, and I'll work up and test a patch.
-- Tim Hockin Systems Software Engineer Sun Microsystems, Cobalt Server Appliances thockin@sun.com - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Tue Oct 23 2001 - 21:00:19 EST