On Wed, Jan 30, 2002 at 01:27:29PM -0600 or sometime in the same epoch, Kent E Yoder scribbled:
> I think the delays in the driver *were* just working around PCI posting
> effects. I tested by removing all the delays and instead putting
> something like:
> writew(val, addr);
> (void) read(addr);
Yep, I has a similar problem when developing olympic, I would write
twice to the same location in very quick succession. This was using
one of the built in locations that the chipset would binary OR to the
current value. So theoretically the second write should have been
OR'ed with the first write, but the second write was being done before
the first write was committed across the pci bus, resulting in only
the second value being stored.
In the end, I rewrote it to combine into a single write.
-- Mike Phillips Linux Token Ring Project http://www.linuxtr.net mailto: mikep@linuxtr.net- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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