> > effects. I tested by removing all the delays and instead putting
> > something like:
> > writew(val, addr);
> > (void) readw(addr);
Ok, now I'm curious about something...
If the readw() above is needed here (it definitely fixes *something*),
what purpose does the volatile below serve?
io.h:122:#define writew(b,addr) (*(volatile unsigned short *)
__io_virt(addr) = (b))X
Is this a sort of "go do this now" command to flush it from the CPU to the
PCI bus, while the readw() makes sure its flushed out of the PCI cache?
> >
> > instead, to flush the PCI cache. Things seem to be happy.
> >
> > Is this the best way to make sure the PCI cache is flushed for writes
that
> > need to happen immediately? I don't see many other drivers doing
it...
Another question is, if the PCI bus is caching like this, how does it
handle adapters which write to one address and read from another for the
same variable? I'm guessing it flushes all writes on a read? This is
exactly what lanstreamer does, and I'm thinking this may have caused
problems before.
Thanks,
Kent
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This archive was generated by hypermail 2b29 : Thu Feb 07 2002 - 21:00:18 EST