On Wed, Feb 06, 2002 at 10:12:31AM -0500, Jakub Jelinek wrote:
> Most sane architectures reserve a thread pointer register (%g6 resp. %g7 on
> sparc, tp on ia64, ppc will use %r2, alpha uses a fast pall call as thread
> "register", s390 uses user access register 0 (and s390x uar 0 and 1), etc.).
> On register starved ia32 there aren't too many spare registers, so %gs is
> used instead.
So the x86 designers have provided all sorts of shadow registers and extensive
high speed caches and the glibc developers deliberately choose to defeat all that
expensive optimization?
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This archive was generated by hypermail 2b29 : Thu Feb 07 2002 - 21:00:53 EST