> If the TSC is affected by HLT, throttling, or C2 power management, the
> TSC is broken (as it is on Cyrix chips, for example.) The TSC usually
> *is* affected by C3 power management, but the OS should be aware of
> C3.
ACPI is irrelevant to the machines in question. This is all APM era stuff
and yes some people change the base clock, not stpclk. The cyrix hlt is
already handled
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This archive was generated by hypermail 2b29 : Sat Feb 23 2002 - 21:00:15 EST