Am Dienstag, 11. Juni 2002 09:43 schrieb David S. Miller:
> From: "David S. Miller" <davem@redhat.com>
> Date: Tue, 11 Jun 2002 00:36:25 -0700 (PDT)
>
> The DMA_ALIGN attribute doesn't work, on some systems the PCI
> cacheline size is determined at boot time not compile time.
>
> Another note, it could be per-PCI controller what this cacheline size
> is. We'll need to pass in a pdev to the alignment interfaces to
> do this correctly.
Could you please explain this ?
I thought this was a problem of a CPU dirtying a cache line
that overlaps with an area being DMAed into. So the determining
factor should be the granularity of the dirty status of the CPU.
Are there really PCI controllers which have to physically write
much more than is transfered ?
Now really puzzeled
Oliver
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