On 7 Aug 2002, Luca Barbieri wrote:
> GDT entries are usually accessed with this pattern:
> * Interrupt: read TSS (for ss0:esp0) and kernel CS/DS
> * Schedule: write TLS, LDT, load FS and GS (either TLS, user DS
> or LDT entry)
> * Return: read user CS/DS
>
> Swapping the TLS and TSS entries causes the GDT entries that are read
> during interrupt and schedule to be in the same cacheline.
yes, this makes perfect sense.
Ingo
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This archive was generated by hypermail 2b29 : Wed Aug 07 2002 - 22:00:36 EST