On Sunday 11 August 2002 09:40, Andrew Morton wrote:
> zone->lock and zone->lru_lock are two of the hottest locks in the
> kernel. Their usage patterns are quite independent. And they have
> just been put into the same structure. It is essential that they not
> fall into the same cacheline.
>
> That could be fixed by padding with L1_CACHE_BYTES. But the problem
> with this is that a kernel which was configured for (say) a PIII will
> perform poorly on SMP PIV. This will cause problems for kernel
> vendors. For example, RH currently ship PII and Athlon binaries. To
> get best SMP performance they will end up needing to ship a lot of
> differently configured kernels.
>
> To solve this we need to know, at compile time, the maximum L1 size
> which this kernel will ever run on.
>
> This patch adds L1_CACHE_SHIFT_MAX to every architecture's cache.h.
>
> Of course it'll break when newer chips come out with increased
> cacheline sizes. Better suggestions are welcome.
I think you're being too paranoid. You pushed the performance degradation
from the PIV to the PIII (because it will tend to hit more cachelines than it
should) and you won't be able to build a kernel that is optimal for the PIII
any more. I'd say that is PIII kernel is *supposed* to suck to some degree
when run on a PIV, otherwise why bother having the PIV option?
I expect the performance difference you're talking about is marginal anyway.
Maybe you've measured it?
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This archive was generated by hypermail 2b29 : Thu Aug 15 2002 - 22:00:24 EST