Changes:
-remove dma reset in stop_{dac,adc}
(from ICH4 manual: contents of all Bus master related registers to be
reset; so, probably some registers are not re-initilized properly on
consecutive re-opening of /dev/dsp ???)
-remove writes to OFF_CIV, instead set LVI relative to CIV
and some stuff that was already in the last diff I send to the list:
-implement a codec ID <-> IO register offset mapping
-in i810_ioctl, case SNDCTL_DSP_CHANNELS: only touch bits 20:21
off GLOB_CNT (multichannel capabilities)
-AMD 8111 has 6 hw channels so I must have mmio (but I don't have
any docs to verify this)
-minor fixes
-- Juergen "George" Sawinski Max-Planck Institute for Medical Research Dept. of Biomedical Optics Jahnstr. 29 D-69120 Heidelberg GermanyPhone: +49-6221-486-308 Fax: +49-6221-486-325
priv. Phone: +49-6221-418 858 Mobile: +49-171-532 5302
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This archive was generated by hypermail 2b29 : Sat Aug 31 2002 - 22:00:25 EST