On Mon, 9 Sep 2002, Linus Torvalds wrote:
> I agree with you, but that is only true for edge-triggered APIC
> interrupts, though - for level-triggered ones we will just re-take the
> interrupt when we unmask it again.
>
> Which is kind of sad. Is there some fast way to read the status of a
> level-trigger irq off the IO-APIC in case it is still pending, and to do
> the mitigation even for level-triggered?
perhaps Remote IRR might help there?
> (Btw, if there is, that would also allow us to notice the "constantly
> screaming PCI interrupt" without help from the low-level isrs)
As an aside, i just had an idea for another way to improve interrupt
handling latency. Instead of walking through all the isrs in the chain,
we can have an isr flag wether it was the source of the irq, and if so we
stop right there and not walk through the other isrs. Obviously taking
into account that some devices are dumb and have no real way of
determining.
Zwane
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This archive was generated by hypermail 2b29 : Sun Sep 15 2002 - 22:00:18 EST