On Thu, Nov 21, 2002 at 01:23:02PM +0000, Dave Jones wrote:
> On Thu, Nov 21, 2002 at 02:10:02PM +0100, Andi Kleen wrote:
>
> > The P4 has 128byte L2 cache lines (2^7). The L1 apparently has smaller lines.
>
> Not mine:
>
> L2 unified cache:
> Size: 512KB Sectored, 8-way associative.
> line size=64 bytes.
>
> Someone (Manfred?) pointed out a chapter in the P4 system programmer guide about
> this last time I brought it up. I forget the reasoning, I'll see if I can dig it out..
The only reference I was able to find was in the Intel Technology Journal,
which says the L2 cache has a 128 byte cache line.
http://developer.intel.com/technology/itj/q12001/articles/art_2.htm
-> "Netburst microarchitecture" -> Level 2 Instruction and Data Cache
"The L2 cache is organized as an 8-way set-associative cache with 128 bytes
per cache line. These 128-byte cache lines consist of two 64-byte sectors.
A miss in the L2 cache typically initiates two 64-byte access requests to the
system bus to fill both halves of the cache line. The L2 cache is a write-back
cache that allocates new cache lines on load or store misses. "
It is refering to the older 256K cached P4, but I doubt they changed it.
Your cache reporting may refer to the 64byte sectors or is just wrong
(would not be the first time that has happened - some P4 versions also
misreported their TLB size)
For cache colouring purposes you need to use the 128 byte unit.
-Andi
-Andi
>
> Dave
>
> --
> | Dave Jones. http://www.codemonkey.org.uk
> | SuSE Labs
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Sat Nov 23 2002 - 22:00:36 EST