Pavel Machek wrote:
> Hi!
>
>
>>>User on cpu1 reads time, communicates it to cpu2, but cpu2 is drifted
>>>-50ns, so it reads time "before" time reported cpu1. And gets confused.
>>>
>>
>>How can you get that communication to happen in < 50 ns?
>
>
> I'm not sure I can do that, but I'm not sure I can't either. CPUs
> snoop each other's cache, and that's supposed to be fast...
>
Even over a 400 MHz FSB you have 2.5 ns cycles. I doubt you can
transfer a cache line in 20 FSB cycles.
-hpa
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This archive was generated by hypermail 2b29 : Mon Dec 23 2002 - 22:00:25 EST