grundler@cup.hp.com (Grant Grundler) writes:
> On Thu, Jan 09, 2003 at 03:35:32PM -0800, Linus Torvalds wrote:
> > The only real reason to worry about BAR sizing is really to do resource
> > discovery in order to make sure that out bridges have sufficiently big
> > windows for the IO regions. Agreed?
>
> yes. And eventually to make sure regions don't overlap.
>
> > And that should be a non-issue especially on a host bridge, since we
> > almost certainly don't want to reprogram the bridge windows there anyway.
>
> Current PARISC servers do not allocate MMIO/IO resources for all PCI devices.
> Only boot devices are configured. Fortunately, default MMIO/IO address
> space assigned to Host bridges seems to work - at least I've not heard
> anyone complain (yet). But no one has tried PCI expansion chassis or
> cards with massive (> 64MB) MMIO BARs.
For what it is worth these cards exist though.
Quadris cards have a 256MB bar, and dolphin cards default to having a 512MB bar.
Both are high performance I/O adapters.
> Because of PCI hotplug, rumor is ia64 firmware folks want to do
> the same thing in the near future.
If someone leaves a big enough hole for hotplug cards I guess it can work...
How you define a potential boot device, and what it saves you to not assign
it resources I don't know.
I am still recovering from putting a 256MB bar and 4GB of ram in a 4GB hole,
with minimal loss on x86, so my imagination of what can be sanely done
on a 64bit arch may be a little stunted..
Eric
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This archive was generated by hypermail 2b29 : Wed Jan 15 2003 - 22:00:31 EST