On Mon, Jan 13, 2003 at 08:03:29PM +0100, Benjamin Herrenschmidt wrote:
> Exactly. My problem right now is with enforcing that 400ns delay on
> non-DMA path as with PCI write posting on one side, and other fancy bus
> store queues etc... you are really not sure when your outb for the
> command byte will really reach the disk.
As a slight tangent, PCI write posting is quite annoying because on some
hardware one simply cannot perform a read immediately after a write,
without pausing for a hardware-specified amount of time.
...but, at the same time, who knows how long the write posting may take,
so one doesn't know how long the delay really needs to be.
It would be nice if there was an arch-specific flush-posted-writes hook
[wmb_mmio() ?], if that was possible on write-posting CPUs. Currently
right now the canonical solution ("MMIO read") doesn't work in some
situations, and I do think we have a solution at all for those "some
situations."
Jeff
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This archive was generated by hypermail 2b29 : Wed Jan 15 2003 - 22:00:47 EST