On Tue, 2003-01-14 at 02:35, Ross Biro wrote:
> Ross Biro wrote:
>
> >>>
> >>> This is technically a spec violation, but it's probably safe. I'm
> >>> going to send an email to a couple of the drive manufacturers and
> >>> see what they think.
> >>>
> >>
> I just heard back from one ide controller chip vendor and they think we
> should disable PCI write posting. From the tone of the response, I
> believe that they may not have thought of this before and it may be a
> problem in their non-opensource drivers as well.
Argh... Well, I don't think that's a solution unfortunately. The
"posting" can be done at various level down the path to the device and
we don't always know how to (or want to) tweak it to disable any kind of
posting. It can be done on P2P bridges, it can be done in the host
bridge (for which we may have no specs in some cases) and it can be done
at the CPU level (not couting the IDE chipset itself that might want to
play tricks).
So what can we do at this point ? I beleive the only sane solution is to
provide that hwif->IOSYNC. Normal PCI-DMA controllers setting it to
dma_base by default, I know what to do for ide-pmac, others will have to
find some way to get it right for their platform (legacy x86 IO ports
might not be a problem as Alan pointed those IOs are fully synchronous).
Maybe we shall initialize that to some default provided by asm/ide.h (I
don't like that much though).
Ben.
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This archive was generated by hypermail 2b29 : Wed Jan 15 2003 - 22:00:49 EST