Ivan Kokshaysky wrote:
> This is rather conservative variant of previous patch:
Looks ok, and the previous patch behaved fine on the hardware
I could test it with. The changes being: to set the cacheline
size only on the "prep_mwi" path (vs much earlier), and allow
cacheline size to be a multiple of the "real" one.
> - assume cacheline size of 32 bytes for all x86s except K7/K8 and P4.
> Actually it's good for 386/486s as quite a few PCI devices do not support
> smaller values.
Given the number of people that questioned that K7/K8/P4 logic,
I'd suggest putting that comment into the pcibios_init() code.
> If you all are fine with it, I can make a 2.4 counterpart.
Yes, having that avoid compile-time config is also important.
Thanks for updating this stuff -- it'll be good to know more
drivers can reduce their PCI/cache overheads.
- Dave
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This archive was generated by hypermail 2b29 : Sun Mar 23 2003 - 22:00:30 EST