Paul:
On 15 May 2003, Paul Fulghum wrote:
> I think I misread your message. Is there a per port resume
> indication? (I'm at home and don't have the specs in front
> of me) I was thinking of the global USBSTS_RD bit.
You can probably find this information in your copy of the specs. Bit 6
of the PORTSC register is Resume Detect. When that bit gets set, the host
controller signals a global resume and presumably sets bit 2 of the USBSTS
register.
> If you can qualify the global USBSTS_RD bit with a per
> port resume indication on a non OC port, then it might
> make sense to do this on the wakeup side.
>
> Pro: you could suspend the controller when appropriate
> without interference from the OC ports
>
> Con: you would be generating a lot of spurious interrupts
> as the global USBSTS_RD is set (incorrectly) by the OC ports.
> Even though you would not actually do the wake, you still
> burn cycles servicing the false interrupts.
I'm not sure about that. For ports in a permanent OC state, the RD bit
would get set just once, so a single interrupt would be generated. When
the host clears the Resume Detect bit in the USBSTS register, it shouldn't
get set again (not until a different port signals a resume). Otherwise a
properly working system would generate continuous interrupts during the
global resume sequence.
That's just guesswork on my part; the spec isn't sufficiently precise to
be certain one way or the other. You can find out pretty easily by
testing the driver on your machine. Just don't do anything in the ISR
when USBSTS_RD is set. Come to think of it, I can try the same thing
here.
> So my inclination is still to nab this on the suspend side.
By a nice coincidence, my system has a 8086:7112 controller -- wired up
correctly and perfectly useable. So I can easily test to make sure that
the final proposed change works okay on a good system.
BTW, I'm not entirely pleased with the size of my test patch. It's a bit
lengthy for something intended mainly to move a delay loop outside an ISR.
But I couldn't think of any simpler way to do it, and once the state
transition code is there it's really no harder to add the 1-second "grace"
periods. So of the three ingredients we've got here (20ms delay outside
of ISR, "grace" periods, checking for OC ports), I don't think we could
make the patch much simpler by eliminating any. What do you think?
Alan Stern
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