Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Jamie Lokier]

Paul Mundt wrote:
> sh (VIPT cache):
> 
> Test separation: 4096 bytes: FAIL - cache not coherent
> Test separation: 8192 bytes: FAIL - cache not coherent
> Test separation: 16384 bytes: pass

A VIVT cache can do that, but I think a VIPT cache should always be coherent.
Do I misunderstand?

-- Jamie
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