Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Jamie Lokier]

Russell King wrote:
> On Mon, Sep 01, 2003 at 11:12:24AM +0100, Jamie Lokier wrote:
> > Russell King wrote:
> > > This looks like an old kernel on your NetWinder.  Later 2.4 kernels
> > > should get this right (by marking the pages uncacheable in user space.)
> > 
> > How do they know which pages to mark uncacheable?  Surely not all
> > MAP_SHARED|MAP_FIXED mappings are uncacheable?
> 
> By looking at the mappings present in the process.  If a process maps the
> same file using MAP_SHARED _and_ we fault the same page of data into two
> or more mappings, we turn off the cache for those pages.

   1. That's not necessary when the virtual addresses are separated
      by some multiple, is it?

   2. The other architectures with incoherent caches set SHMLBA to the
      multiple, and they don't do anything special in
      update_mmu_cache(), so MAP_FIXED can create incoherent mappings.

      Is there any special reason why ARM is different?

> I've tested on several silicon revisions of StrongARM-110's:
> - H appears buggy (reports as rev. 2)
> - K appears fine (reports as rev. 2)
> - S appears buggy (reports as rev. 3)

It's possible that all of them are buggy, but the write buffer test
doesn't manage to get writes into the buffer with the exact timing
needed to trigger it.  Unfortunately, while the write buffer test does
pretty much guarantee a store/store/load instruction sequence, because
it's generic it can't guarantee how those are executed in a
superscalar or out of order pipeline.

> So it seems your test program finds problems which DaveM's aliastest
> program fails to detect...  Gah. ;(

Well, it's good to know it was useful :/

Thanks,
-- Jamie
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