Further, PCI posting: a writeb() / writew() / writel() will not be flushed immediately to the processor. The CPU and/or PCI bridge may post (delay/combine) such writes. I do not think this is a desireable effect, for PCI config register accesses.Good point. Fixed.
Here I'm somehwat lost. Writes to uncacheable RAM will be in program order and never combined. The bridge itself should not post writes to config space. So it's a matter of pushing the write to the processor
bus, a PCI read looks very heavy for this. Isn't there a more
lightweight solution ?
Regards,
Gabriel