afaics all Intel and AMD cpus with more than say 32 or 64 TLB's areDoes AMD document how the CAM filter actually works? x86-64 writes into the 4th level page table during a context switch and if I understand the patent description correctly, this defeates the flush filter and forces a full flush during a context switch.
actually 64 bit capable.... so obviously you run a 64 bit kernel there. (and amd64 even has that sweet CAM filter on the tlbs to mitigate the
effect even if you run a 32 bit kernel)