[PATCH] FRV accidental TLB entry write-protect fix

[David Howells]

The attached patch stops the FRV kernel-instruction-TLB-miss handler from
setting the write-protect bit on a mapping entry when punting an entry from
the mapping fast cache registers (DAMR1/IAMR1) to the TLB.

This patch derives the WP value from the DAMPR1 register (which actually has
a WP bit) rather than the IAMPR1 register (which does not).

Signed-Off-By: David Howells <dhowells@xxxxxxxxxx>
---
warthog>diffstat frv-nowp-2610rc3.diff 
 tlb-miss.S |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff -uNr linux-2.6.10-rc3-mm1-mmcleanup/arch/frv/mm/tlb-miss.S linux-2.6.10-rc3-mm1-misc/arch/frv/mm/tlb-miss.S
--- linux-2.6.10-rc3-mm1-mmcleanup/arch/frv/mm/tlb-miss.S	2004-12-13 17:33:50.000000000 +0000
+++ linux-2.6.10-rc3-mm1-misc/arch/frv/mm/tlb-miss.S	2004-12-13 19:28:21.000000000 +0000
@@ -184,8 +184,8 @@
 	movgs		gr31,tplr			/* set TPLR.CXN */
 	tlbpr		gr31,gr0,#4,#0			/* delete matches from TLB, IAMR1, DAMR1 */
 
-	movsg		iampr1,gr31
-	ori		gr31,#xAMPRx_V|DAMPRx_WP,gr31	/* entry was invalidated by tlbpr #4 */
+	movsg		dampr1,gr31
+	ori		gr31,#xAMPRx_V,gr31		/* entry was invalidated by tlbpr #4 */
 	movgs		gr31,tppr
 	movsg		iamlr1,gr31			/* set TPLR.CXN */
 	movgs		gr31,tplr
-
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