On Wed, 5 Jan 2005, Prakash K. Cheemplavam wrote:
...
DEBUG: pci_fixup_nforce2() called.
DEBUG: nForce2 revision byte = 0xC1.
DEBUG: fixed value = 0x9F01FF01.
DEBUG: current value = 0x8F0FFF01. <---------------
...
So that means, that the device doesn't have the "C1 Halt Disconnect"
enabled at that point, and, though, no fixup is done. However, if you take
a closer look at the result of "lspci -xxx" (attached as "lspci-xxx.log"),
00:00.0 Host bridge: nVidia Corporation nForce2 AGP (different version?) (rev c1)
...
60: 08 00 01 20 20 00 88 80 10 00 00 00 01 ff 0f 9f <-------
...
you'll notice, that all of a sudden that bit 28 of PCI.0x6c *is set!! That
means, that sometimes later, after the pci_fixup_nforce2() is called,
something, smewhere, somehow has to set the bit to 1. But this part in the
arch/i386/pci/fixup.c prevents it.
/*
* Apply fixup only if C1 Halt Disconnect is enabled
* (bit28) because it is not supported on some boards.
*/
vvvvvvvvvvvvvvvvv
if ((val & (1 << 28)) && val != fixed_val) {
printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
pci_write_config_dword(dev, 0x6c, fixed_val);
}
So my question is: Is the condition necessary? If there really are boards,
that don't support this, then is would probably have to be a more
sophisticated test, or the fixup would have to be called again later, when
the flag is set. BTW.: Any clue on what could possibly set the flag?
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