Re: increased translation cache footprint in v2.6

[Benjamin Herrenschmidt]

On Mon, 2005-06-27 at 16:35 -0400, Dan Malek wrote:
> On Jun 27, 2005, at 3:50 PM, David S. Miller wrote:
> 
> > I think you're making this problem more complex than it really
> > is.  There is no reason at all to hold page tables for the direct
> > physical memory mappings of lowmem if you have any control whatsoever
> > over the TLB miss handler.
> 
> I'm not one to make it more complex, I just want to cover
> all of the possibilities :-)  The "compute kernel" part of
> it needs to be generic for all of the possibilities.   Like I mentioned.
> we have a quite configurable address space for mapping text,
> data, IO, and uncached spaces.  In addition, we have execute
> in place out of flash and other embedded custom options.
> I was hoping to find a solution where the kernel TLBs could
> be dynamically loaded as well, with the standard look up
> algorithm.  Yes, I still need a kernel path for the special
> case processing of other than 4K pages, but it would be nice
> to keep that generic as well.

Can't you put the "8Mb page" flag at the PMD level and use normal kernel
page tables ? You'll have to fill PMD entries two by two but that
shouldn't be too difficult.

You can then have the kernel linear mapping use 8Mb pages, along with
some "block IO" translations and leave the rest to normal 4k page tables

Ben.


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