RE: [PATCH] 2.6.14-rc3 ixp4xx_copy_from little endian/alignment

[John Bowler]

From: David Vrabel [mailto:dvrabel@xxxxxxxxxx]
>It appears that the NSLU2 only has the flash on the expansion bus which 
>is why you believe it's a flash specific problem.

Which would also explain why a flash specific solution works...  I'll
try an experiment without the XOR on the address and with data coherency.

The issue here is whether that's the right answer for hypothetical other
IXP4XX LE systems which have both flash and non-flash peripherals on EXP.

Still, it doesn't much matter - NSLU2 doesn't have such devices (so far as
I know - i.e. I believe that your statement about there being nothing else
on the EXP bus is correct) and we implemented this patch for NSLU2, even
though it isn't NSLU2 specific.

>Data coherency can be set on a per 1 Mibyte page basis so all other (APB 
>and PCI) peripherals would continue to use address coherency and thus 
>would continue to function as they are now.

Ok... so I'll try to find a way to do this in the board level code, or
maybe better in the IXP4XX setup (drivers/mtd/maps/ixp4xx.c?)

It's worth considering that, so far as I can see, nothing which uses
drivers/mtd/maps/ixp4xx.c will currently work in LE unless it is already
setting data coherency on the flash addresses.  Is NSLU2 the first IXP4XX
system to run LE and to access the flash (from a running system, not from
the boot loader?)

John Bowler <jbowler@xxxxxxx>

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