IOMMU and scatterlist limits

[Pierre Ossman]

I'm writing a PCI driver for the first time and I'm trying to wrap my
head around the DMA mappings in that world. I've done a ISA driver which
uses DMA, but this is a bit more complex and the documentation doesn't
explain everything.

What I'm particularly confused about is how the IOMMU should be handled
with regard to scatterlist limits. My hardware cannot handle
scatterlists, only a single DMA address. But from what I understand the
IOMMU can be very similar to a normal "CPU" MMU. So it should be able to
aggregate pages that are non-continuous in physical memory into one
single block in bus memory. Now the question is what do I set
nr_phys_segments and nr_hw_segments to? Of course the code also needs to
handle systems without an IOMMU.

Rgds
Pierre
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