Re: Uses for memory barriers

[Paul E. McKenney]

On Wed, Sep 20, 2006 at 05:48:00AM +1000, Nick Piggin wrote:
> Paul E. McKenney wrote:
> >On Wed, Sep 20, 2006 at 04:48:45AM +1000, Nick Piggin wrote:
> >Sooner or later, the cacheline comes to the store queue, defining
> >the ordering.  All changes that occurred in the store queue while
> >waiting for the cache line appear to other CPUs as having happened
> >in very quick succession while the cacheline resides with the store
> >queue in question.
> >
> >So, what am I missing?
> 
> Maybe I'm missing something. But if the same CPU loads the value
> before the store becomes visible to cache coherency, it might see
> the value out of any order any of the other CPUs sees.

Agreed.  But the CPUs would have to refer to a fine-grained synchronized
timebase or to some other variable in order to detect the fact that there
were in fact multiple different values for the same variable at the same
time (held in the different store queues).

If the CPUs looked only at that one single variable being stored to,
could they have inconsistent opinions about the order of values that
this single variable took on?  My belief is that they could not.

						Thanx, Paul
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