Re: Uses for memory barriers

[Alan Stern]

On Mon, 16 Oct 2006, Paul E. McKenney wrote:

> > The reason I don't like "conditionally precedes" is because it suggests
> > the ordering is not automatic even in the single-CPU case.
> 
> Aside from MMIO accesses, why would you be using memory barriers in the
> single-CPU case?

Obviously you wouldn't.  But you might be fooled into doing so if you saw
the term "conditionally precedes" together with an explanation that the
"condition" requires a memory barrier to be present.  You might also draw
this erroneous conclusion if you are on an SMP system but your variable is
accessed by only one of the CPUs.

>  If you aren't using memory barriers, then just plain
> "precedes" works fine -- "conditionally precedes" applies only to memory
> barriers acting on normal memory (again, MMIO is handled specially).

No, no!  Taken out of context this sentence looks terribly confused.  
Read it again and you'll see what I mean.  (Think about what it says for
people who don't use memory barriers on SMP systems.)  Here's a much more
accurate statement:

	If you are in the single-CPU case then just plain "precedes" 
	works fine for normal memory accesses (MMIO is handled
	specially).

	But when multiple CPUs access the same variable all ordering
	is "conditional"; each CPU must use a memory barrier to
	guarantee the desired ordering.

Alan

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