Re: [patch] Pad irq_desc to internode cacheline size

[Eric W. Biederman]

Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx> writes:

> This will consume nearly 4k per irq won't it?  What is the upper bound
> here, across all configs and all hardware?
>
> Is VSMP the only arch which has ____cacheline_internodealigned_in_smp
> larger than ____cacheline_aligned_in_smp?

Ugh. We set internode aligned to 4k for all of x86_64.

I believe this ups our worst case memory consumption for
the array from 1M to 32M.  Although the low end might be 2M.
I can't recall if an irq_desc takes one cache line or two
after we have put the cpu masks in it.

My gut feel says that what we want to do is delay this until
we are dynamically allocating the array members.  Then we can at
least have the chance of allocating the memory on the proper NUMA
node, and won't need the extra NUMA alignment.

I'm not at all certain I'm impressed by an architecture that has
4K aligned cache lines.  That seems terribly piggy.  We might as
well do distributed shared memory in software on a cluster...

Eric
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