PCI-Express root complex quirk in virtual P2P bridge

[Kumar Gala]

I was hoping to get some guidance on how to handle a quirk in how the  
virtual P2P bridge works on some embedded PowerPC PCI-Express root  
complex controllers.  In the controllers I'm dealing with when we  
change PCI_PRIMARY_BUS in pci_scan_bridge the ability to send config  
cycles to the controller itself becomes effected.  The controller  
only sends config cycles internally if the bus # in the config cycle  
matches the PCI_PRIMARY_BUS.  We end up going from being 0 to 3 in  
the particular setup and at the point we set PCI_PRIMARY_BUS to 3 we  
are no longer able to send internal config cycles.

What we need is that either a quirk or pcibios code needs to get call  
right after we set PCI_PRIMARY_BUS so we can fixup the bus number  
relationship.  I was wondering if anyone had suggestions on how best  
to handle this.

thanks

- k
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