Re: [PATCH] trim memory not covered by WB MTRRs

[Jesse Barnes]

On Tuesday, June 26, 2007 8:02:49 am Andi Kleen wrote:
> On Mon, Jun 25, 2007 at 04:36:52PM -0700, Jesse Barnes wrote:
> > On Monday, June 25, 2007 4:34:33 Andi Kleen wrote:
> > > > This patch fixes a bug in the last patch that caused the code to
> > > > run on non-Intel machines (AMD machines apparently don't need it
> > >
> > > Actually the problem can happen on AMD too, but the symptoms can
> > > be different and there can be more wrong than just the MTRRs.
> >
> > I should have been more specific in the changelog.  My understanding is
> > that AMD systems don't need it for memory above 4G, and since the code
>
> AMD systems need MTRRs to get cached memory too, or what is your point?

My point is that yes, this problem can happen on AMD, but the code doesn't 
handle the problems that AMD systems might have, since it doesn't look for 
problems in low memory (e.g. if you have an AMD system with 6G of memory, the 
code will probably trim everything above 4G since it doesn't know about the 
new AMD mapping stuff from RevE), as Eric pointed out.

Both you and Eric say you've seen AMD systems with problems, but handling them 
would make the code more complex than it is now, and I haven't seen the 
actual reports (memory maps & MTRR setups) so I can't really fix them anyway.  
And since this patch solves real problems as-is, it seems like we should push 
it upstream then rework it, if necessary (i.e. real user machines with this 
problem) later.

What do you think?

Jesse
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