Re: about cs5536 interrupt ack

[Maciej W. Rozycki]

On Wed, 11 Jul 2007, Songmao Tian wrote:

> > Huh?  Have you managed to find an 8259A clone *that* broken?  So what does
> > it return if you write 0xc to the address 0x20 in the I/O port space and
> > then read back from that location?  You should complain to the 
> >   
> 
> It's the value of IRR, so guess IRR. AMD has well documented cs5536, I
> appreciate that.

 Indeed.  I am surprised they have decided to drop the poll command -- it 
surely does not require much logic as it mostly reuses what's used to 
produce the vector anyway and it is commonly used when 8259A 
implementations are interfaced to non-i386 processors.  PPC is another 
example.

> > More or less -- 3-5 should probably be the outcome of a single read
> > transaction from the north bridge.  I.e. you issue a read to a "magic"
> > location, 3-5 happen, and the data value returned is the vector presented by
> > the interrupt controller on the PCI bus.
> >   
> yeah, we can implement a register in north bridge.

 Strictly speaking it would not be a register, but a "PCI INTA address 
space" much like PCI memory or I/O port address spaces.  Though as the 
former ignores addresses driven on the bus, the space occupied does not 
have to be extensive -- I would assume whatever slot size is available 
with the address decoder you have implemented would do.

> > You can still dispatch interrupts manually by examining the IRR register,
> > but having a way to ask the 8259A's prioritiser would be nice.  Although
> > given such a lethal erratum you report I would not count on the prioritiser
> > to provide any useful flexibility...
> >   
> yeah, that's a straight thought, tried but failed:(, patch followed.

 You may have to modify other functions from arch/mips/kernel/i8259.c; 
yes, this makes the whole experience not as pretty as one would hope...

  Maciej
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