Re: ICH8 CF timeout (regression)...

[Tejun Heo]

Kristen Carlson Accardi wrote:
> In the data sheet in section 5.15.2.3 it describes a value of map.mv of
> 1 as meaning that the SATA controller is emulating the logical secondary
> channel, and the PATA channel will be the primary.  For a value of
> map.mv == 2, we have the SATA controller being primary, and the PATA
> is secondary.  So, if I'm understanding the way ata_piix does mapping, 
> it seems like for a value of 2, we should have [p0, p2, ide, ide] and 
> for a value of 1 we should have [ide, ide, p0, p2] - although for ICH8M 
> it seems like 1 should not be a valid value. My reading the ICH8 spec is 
> that ICH8M only implements a map value of 2, and 1 should be reserved 
> (see section 12.1.33).

Alright, thanks a lot.

-- 
tejun
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