Re: [patch 0/8] Immediate Values

[Arjan van de Ven]

> > 
> > I have a concern; you seem to be patching potentially "live" code....
> > 
> > there are basically two options
> > 1) you run the risk of triple faulting (patching an instruction while
> > some other core/cpu may be decoding it may cause a triple fault)
> > 2) you do an IPI to all other cpus and prevent them from executing any
> > code except a small loop during the patching... this is expensive.
> > 
> > To be honest, neither sound very attractive to me ;(
> > 
> 
> Yup, the concern is appropriate. That's why I dealt with it in the
> "Immediate Values - i386 Optimization" patch. (I guess your concern
> is specific to i386, x86_64 and ia64).

it's specific to all smp architectures I suppose
> 
> I have currently only implemented the i386 optimization, but x86_64 and
> ia64 should be similar.
> 
> The triple fault in question is discussed in Intel's errata under the
> title "Centrino Duo Processor Technology Specification Update, AH33.
> Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected
> Instruction Execution Results." (if you refer to something else, please
> tell me).

Core2DUO is only one generation of Intel processors; however I know that
several other (if not all of them) have issues with this kind of thing
in ring 0; all subtly different ;(

All other alternatives are ok right now (they all run in UP mode),
but... I'm just very nervous about the amount of CPU errata in this kind
of scenario. And I'm not just talking Intel, I wouldn't be surprised if
the other x86 CPU vendors also have issues with this; I don't know how
well they specify their errata though..


-- 
if you want to mail me at work (you don't), use arjan (at) linux.intel.com
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