Here's how BARs work ... when you write 0xffffffff to the BAR, itThanks for the detailed explanation.
ignores all the set bits that are less than the size of the BAR. So,
assuming this is a 256MB BAR (like my G33 is), what ends up written to
this BAR is 0xf0000000. Now, because this is graphics, apparently it's
special and embedded in the chipset, even though it looks like it's a
PCI device. So it actually gets priority over MMCONFIG which is also
mapped to 0xf0000000.
For your case of a 64-bit BAR, you could write 0xffffffff to the high
32-bits first, then write to the low 32-bits, then reset the low, then
high bits, and you'd avoid the problem. But the G33 has a 32-bit BAR
with the same problem, so it won't work for that case.
BARs that are behind bridges don't have this problem (they can't decode
memory accesses that aren't forwarded to them). BARs on devices which
have memory IO disabled also don't have theis problem, but disabling
devices has its problems (as does probing BARs for active devices anyway
...).
I'm really not clear on the purpose of your patchset. Was it all to
address this one problem?