Re: [Fwd: Re: [PATCH 0/5]PCI: x86 MMCONFIG]

[Andi Kleen]

Robert Hancock <hancockr@xxxxxxx> writes:

> First off, I would like to see confirmation from the horses's mouths
> here (namely AMD,

AMD publicly releases errata sheets/data sheets for their PCI bridges
(check their website).  I haven't checked the 8132 errata for this
though. Not sure it implements MMCONFIG at all.

However the PCI Express chipsets typically do implement 
their own MMCONFIG aperture.

> The case of the device built into the K8 northbridge that's
> unreachable by MMCONFIG kind of makes sense, 

The internal northbridge devices on K8 are not reachable through
mmconfig. While BIOS are supposed to express this in MCFG by excluding
that bus many don't. That was the original reason I added the
type1<->mcfg sanity check. It catches the K8 case fine.

> since the northbridge is
> what's translating the MMCONFIG memory access into config accesses. 

The way it works on K8 systems is that the CPU internal northbridge
knows nothing about MMCONFIG, but that the external chipsets
implement an MMCONFIG aperture on their own outside the northbridge.

If you have multiple bridges like some SLI K8 setups that could
be multiple ones.

This has changed on the Quad Core Fam10h CPUs BTW -- there the
NB can deliver an single mmconfig aperture that is translated
to appropiate transactions on the Hypertransport link.

What might happen with K8 and 8132 (I'm speculating here) is that 
they got a PCI Express chipset that implements an MMCONFIG 
aperture for its devices, but the system also has a PCI-X 8132
bridge and the MMCONFIG aperture inside the chipset doesn't
support talking to the 8132 which might be "upstream" in the HT
topology. And the BIOS' MCFG doesn't tell Linux that.

-Andi


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