Re: K8, EFFICEON and CORE2 support the cmovxx instructions.
From: Alexander van Heukelum
Date: Sat Mar 15 2008 - 17:07:01 EST
On Sat, 15 Mar 2008 21:18:16 +0100, "H. Peter Anvin" <hpa@xxxxxxxxx>
said:
> Alexander van Heukelum wrote:
> > K8, EFFICEON and CORE2 support the cmovxx instructions.
> >
> > Instead of listing the cpu's that have support for the
> > cmovxx instructions, list the cpu's that don't.
> >
> > Signed-off-by: Alexander van Heukelum <heukelum@xxxxxxxxxxx>
> > ---
> >
> > A bit of playing resulted in:
> >
> > CPUS="M386 M486 M586 M586TSC M586MMX M686 MPENTIUMII MPENTIUMIII"
> > CPUS=$CPUS" MPENTIUMM MPENTIUM4 MK6 MK7 MK8 MCRUSOE MEFFICEON"
> > CPUS=$CPUS" MWINCHIPC6 MWINCHIP2 MWINCHIP3D MGEODEGX1 MGEODE_LX"
> > CPUS=$CPUS" MCYRIXIII MVIAC3_2 MVIAC7 MPSC MCORE2"
> >
> > for cpu in $CPUS
> > do
> > echo "CONFIG_${cpu}=y" > testconfig
> > make ARCH=i386 allnoconfig KCONFIG_ALLCONFIG=testconfig > /dev/null
> > echo ${cpu} >> result
> > grep X86_CMOV .config >> result
> > echo >> result
> > done
> >
> > I'm quite sure that K8, EFFICEON and CORE2 support HAVE_CMOV, but
> > they did not set X86_CMOV.
> >
>
> Crusoe has CMOV as well.
Hi hpa,
I believe you... and the Makefile_32.cpu: it gets a -march=i686. I
also found out that I missed X86_ELAN, which is treated as a i486.
Also, MGEODE_LX does not get any optimization flags. I think that
is unintentional, but what should they be?
And MPSC (Intel P4 / older Netburst based Xeon) depends on X86_64.
I would be very surprised if that one could not run 32-bit code,
though. What flags should that one get?
Thanks for pointing out I missed Crusoe. As a punishment you
can answer my questions ;).
Greetings,
Alexander
--
Alexander van Heukelum
heukelum@xxxxxxxxxxx
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