Re: [patch 0/6] AMD C1E aware idle support

[Len Brown]

On Thu, 12 Jun 2008, Thomas Gleixner wrote:

> AMD CPUs with C1E support are currently excluded from high resolution
> timers and NOHZ support. The reason is that C1E is a BIOS controlled
> C3 power state which switches off TSC and the local APIC timer. The
> ACPI C-State control manages the TSC/local APIC timer wreckage, but
> this does not include the C1 based ("halt" instruction) C1E mode. The
> BIOS/SMM controlled C1E state works on most systems even without
> enabling ACPI C-State control.

What a mess.

What is the measured power savings that justifies this effort?

While I'm okay with platform specific idle states,
I'm not okay with the use of therm C1E here.

C1E has been shipped for many years on Intel processors
and it is completely transparent to the OS.

If AMD now has their own C1E and it breaks the OS,
please call is something like AMD_C1E to make it
totally clear in shared files like process.c
that consulting that variable or running that routine
on Intel hardware would be a Linux bug.

thanks
-Len

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