Re: [patch 0/3] fastboot patches series 1

[Andi Kleen]

Arjan van de Ven <arjan@xxxxxxxxxxxxx> writes:
>
> One possible theory is that we now run on both cpus and if they're out
> of sync timewise, things like delays suddenly are shorter than expected
> if time jumps around....

On systems with non synchronized TSC the clocksource watchdog tends
to disable the TSC time source only quite late in boot (on my systems
typically even after kernel boot). So yes this could be a problem.

However he has a AMD QC system where the TSCs are synchronized on the
hardware level and there's also no message from the watchdog disabling
TSC, so this isn't the problem causing this issue. Must be something else.

-Andi

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