Re: [PATCH] x86 (64): make calibrate_APIC_clock() SMI-safe (take 2)

[Olaf Dabrunz]

On 25-Jul-08, Martin Wilck wrote:
> I wrote:
>
>> This patch fixes this by two separate measures:
>>   a) make sure that no significant interruption occurs between APIC and
>>      TSC reads
>>   b) make sure that the measurement loop isn't significantly longer
>>      than originally intended.
>
> Here is a new, simplified version of our patch that only uses measure a).
> We verified that this is sufficient for accurate calibration.
>
> If we fail to determine the start or end time of the calibration correctly 
> 10 times in a row, we will print a critical error message and go on. One 
> might as well argue that this should cause a kernel panic (it is impossible 
> to run on the CPU for only a few cycles without being interrupted by an 
> SMI!), but Cyrill probably won't agree.

Note that the SMIs may be triggered when the APIC is read. This may
change after the first (or the first few) SMIs have been triggered. So
the "too many SMIs" case during the calibration does not necessarily
mean that the system can not run normally after the calibration is done.

This is why I would prefer the solution with the error message.

Regards,

-- 
Olaf Dabrunz (od/odabrunz), SUSE Linux Products GmbH, NÃrnberg

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