Re: 2.6.27-rc3: 'APIC error on CPU1: 00(40)', but only on resume!

[Maciej W. Rozycki]

On Thu, 21 Aug 2008, Vegard Nossum wrote:

> I've also seen this a lot, so I have now written (I think) such a
> debug patch (it's very crude) and tested it on my laptop, which
> exhibits this problem.
[...]
> APIC error on CPU0: 00(40)
> Last 16 APIC writes:
[...]
> The order is from oldest (0) to newest (15) write. I don't see any
> writes to ICR in there, which means that IPIs can be ruled out? It
> seems that it is the write to Timer that causes it. In another place,
> we have this:

 You are correct about the ICR -- IPIs are unlikely to be a problem 
because only a couple of predefined vectors are used.  Besides, they are 
normally critical enoug for the system to become unstable if unhandled.

 Otherwise there is no correlation between the sequence of APIC writes and
an error triggering -- a bad vector in a LVT or interrupt redirection
entry will be reported whenever its associated interrupt line gets active
even though the entry might have been initialised long ago.  Depending on
the device signalling hardware interrupts may quite often be ignored for a
long time without affecting the stability of the rest of the system.

  Maciej
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