Re: [PATCH] SiS55x, another x86 CPU

[Andi Kleen]

Hans Schou <linux@xxxxxxxx> writes:


> flags           : fpu tsc cx8 mmx
>
> Instruction and data cache is 8KB each it says in the datasheet. I'm
> not sure but it does not look like it is written in dmesg.
>
> ACPI sleep supports S1 S2 S3 S4 S5.
>
> CPU power states supports C0 C1 C2 C3.
>
> See attachment. (I hope it gets here!)

Your attachment seems to be windows line end damaged.
Also the changes are so small that it's not worth adding a CONFIG
for it. Just add it unconditionally.
And hardcoding the cache size for all of SiS seems a bit extreme.
What happens when SiS ever brings out another part with different caches?
Ideally figure out some way to detect this particular CPU and only
use 8 KB only for that. Alternatively ignore it (there's nothing
really in the kernel that uses the cache sizes anyways)

-Andi

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