Re: [PATCH 16/16 v6] PCI: document the new PCI boot parameters

[Zhao, Yu]

Greg KH wrote:
> On Wed, Oct 22, 2008 at 04:45:31PM +0800, Yu Zhao wrote:
> >  Documentation/kernel-parameters.txt |   10 ++++++++++
> >  1 files changed, 10 insertions(+), 0 deletions(-)
> >
> > diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
> > index 53ba7c7..5482ae0 100644
> > --- a/Documentation/kernel-parameters.txt
> > +++ b/Documentation/kernel-parameters.txt
> > @@ -1677,6 +1677,16 @@ and is between 256 and 4096 characters. It is defined in the file
> >  		cbmemsize=nn[KMG]	The fixed amount of bus space which is
> >  				reserved for the CardBus bridge's memory
> >  				window. The default value is 64 megabytes.
> > +		assign-mmio=[dddd:]bb	[X86] reassign memory resources of all
> > +				devices under bus [dddd:]bb (dddd is the domain
> > +				number and bb is the bus number).
> > +		assign-pio=[dddd:]bb	[X86] reassign io port resources of all
> > +				devices under bus [dddd:]bb (dddd is the domain
> > +				number and bb is the bus number).
> > +		align-mmio=[dddd:]bb:dd.f  [X86] relocate memory resources of a
> > +				device to minimum PAGE_SIZE alignment (dddd is
> > +				the domain number and bb, dd and f is the bus,
> > +				device and function number).
>
> This seems like a big problem.  How are we going to know to add these
> command line options for devices we haven't even seen/known about yet?
>
> How do we know the bus ids aren't going to change between boots (hint,
> they are, pci bus ids change all the time...)
>
> We need to be able to do this kind of thing dynamically, not fixed at
> boot time, which seems way to early to even know about this, right?
>
> thanks,
>
> greg k-h

Yes, I totally agree. Doing things dynamically is better.

The purpose of these parameters is to rebalance and align resources for 
device that has BARs encapsulated in various new capabilities (SR-IOV, 
etc.), because most of existing BIOSes don't take care of those BARs.

If we do resource rebalance after system is up, do you think there is 
any side effect or impact to other subsystem other than PCI (e.g. MTRR)?

I haven't had much thinking on the dynamical resource rebalance. If you 
have any idea about this, can you please suggest?

Regards,
Yu
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