Re: [PATCH][retry 2] Conform L3 Cache Index Disable to Linuxstandards From: Eric Lammerts <eric@lammerts.org>

[Andrew Morton]

On Fri, 20 Feb 2009 15:50:47 -0600
Mark Langsdorf <mark.langsdorf@xxxxxxx> wrote:

> Add ABI Documentation entry and fix some /sys directory formating
> issues with the L3 Cache Index Disable feature for future AMD
> processors. __Add a check to disable it for family 0x10 models
> that do not support it yet.

This change clashes with (what I assume to be) Rusty changes in
linux-next's arch/x86/kernel/cpu/intel_cacheinfo.c:

--- /tmp/1	2009-02-20 14:41:06.000000000 -0800
+++ /tmp/2	2009-02-20 14:40:52.000000000 -0800
@@ -24,7 +24,8 @@
 
 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
 {
-	int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
+	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
+	int node = cpu_to_node(cpumask_first(mask));
 	struct pci_dev *dev = NULL;
 	ssize_t ret = 0;
 	int i;
@@ -58,7 +59,8 @@
 store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
 		    size_t count)
 {
-	int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
+	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
+	int node = cpu_to_node(cpumask_first(mask));
 	struct pci_dev *dev = NULL;
 	unsigned int ret, index, val;
 

I think those chagnes will need to be carried forward into the new
code.

I made that change when applying this patch locally.  If Ingo applies
this to his tree, Stephen gets to do the same fix for linux-next
integration.

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