Re: [PATCH] pci: enable MSI on 8132

[Grant Grundler]

On Sat, Feb 21, 2009 at 12:58:31AM -0800, Eric W. Biederman wrote:
...
> The difference is that there is a magic address on x86 that all MSI
> cycles are sent to.  I think it is 0xfffe0000.

arch/x86/include/asm/msidef.h:#define MSI_ADDR_BASE_LO          0xfee00000

Intel spells out the details in:
    http://www.intel.com/products/processor/manuals/index.htm

"Volume 3A: System Programming Guide, Part 1"
See chapter "9.4 LOCAL APIC"

>  In an msi to HT
> mapping capability it is necessary to program in the address to listen
> for msi packets.  That is very much an arch dependent thing.

Indeed. parisc and (AFAIK) alpha have the same ability but use completely
different address ranges depending on the chipset as well.

thanks,
grant
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