Re: [PATCH 1/2] CPUFREQ: Enable acpi-cpufreq driver for VIA/Centaur CPUs

[Michael S. Zick]

On Mon June 8 2009, Matthew Garrett wrote:
> On Mon, Jun 08, 2009 at 09:25:09AM -0500, Michael S. Zick wrote:
> > On Mon June 8 2009, Harald Welte wrote:
> > > The VIA/Centaur C7, C7-M and Nano CPU's all support ACPI based cpu p-states
> > > using a MSR interface.  The Linux driver just never made use of it, since in
> > > addition to the check for the EST flag it also checked if the vendor is Intel.
> > >
> > 
> > It looks like we should modify (conditional on ...MVIAC7 at build, model='d' runtime)
> > the acpi-cpufreq controls to deal properly with the Model-D adaptive controller.
> 
> Can't make it build-time dependent - distribution kernels may not 
> explicitly support the C7. It's valid to have a vendor=centaur 
> conditional that turns off any adaptive control if appropriate ACPI 
> methods are present.
> 

A valid point.

I haven't looked yet, but I think we have advanced to the point where the
'VIA hack' for cache-line size can also go away.
Now that the pci-cache-line-size setting is being done differently.
(currently a proposed change).

The C7(xxxx) is 99 44/100% a Pentium-M with minor differences.
(Like the power/thermal/freq adaptive controller on the "D" models.)

Mike

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