Re: [RESEND][ PATCH -tip -v9 1/7] x86: instruction decoder API

[H. Peter Anvin]

Masami Hiramatsu wrote:
> Add x86 instruction decoder to arch-specific libraries. This decoder
> can decode x86 instructions used in kernel into prefix, opcode, modrm,
> sib, displacement and immediates. This can also show the length of
> instructions.
> 
> This version introduces instruction attributes for decoding instructions.
> The instruction attribute tables are generated from the opcode map file
> (x86-opcode-map.txt) by the generator script(gen-insn-attr-x86.awk).
> 
> Currently, the opcode maps are based on opcode maps in Intel(R) 64 and
> IA-32 Architectures Software Developers Manual Vol.2: Appendix.A,
> and consist of below two types of opcode tables.
> 
> 1-byte/2-bytes/3-bytes opcodes, which has 256 elements, are
> written as below;
> 
>  Table: table-name
>  Referrer: escaped-name
>  opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
>   (or)
>  opcode: escape # escaped-name
>  EndTable
> 
> Group opcodes, which has 8 elements, are written as below;
> 
>  GrpTable: GrpXXX
>  reg:  mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
>  EndTable
> 
> These opcode maps do NOT include most of SSE and FP opcodes, because
> those opcodes are not used in the kernel.
> 
> Signed-off-by: Masami Hiramatsu <mhiramat@xxxxxxxxxx>
> Signed-off-by: Jim Keniston <jkenisto@xxxxxxxxxx>
> Cc: H. Peter Anvin <hpa@xxxxxxxxx>
> Cc: Steven Rostedt <rostedt@xxxxxxxxxxx>
> Cc: Ananth N Mavinakayanahalli <ananth@xxxxxxxxxx>
> Cc: Srikar Dronamraju <srikar@xxxxxxxxxxxxxxxxxx>
> Cc: Ingo Molnar <mingo@xxxxxxx>
> Cc: Frederic Weisbecker <fweisbec@xxxxxxxxx>
> Cc: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> Cc: Vegard Nossum <vegard.nossum@xxxxxxxxx>
> Cc: Avi Kivity <avi@xxxxxxxxxx>
> Cc: PrzemysÅaw PaweÅczyk <przemyslaw@xxxxxxxxxxxx>
> ---
> 

The decoder looks good by now.

Acked-by: H. Peter Anvin <hpa@xxxxxxxxx>

	-hpa
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