[RFC] Load cache_aligned sections, cache aligned (VIA, some Intel, others?)

[Michael S. Zick]

The expected size of the processor cache line size is set
in the Kbuild menu by selection of the processor (sort-of).

How about telling the loader to cache-line align the cache_aligned sections?
This define comes in via (no pun intended): arch/x86/include/asm/cache.h

diff --git a/arch/x86/kernel/vmlinux_32.lds.S b/arch/x86/kernel/vmlinux_32.lds.S
index 62ad500..26f68a5 100644
--- a/arch/x86/kernel/vmlinux_32.lds.S
+++ b/arch/x86/kernel/vmlinux_32.lds.S
@@ -82,7 +82,7 @@ SECTIONS
        *(.data.idt)
   }

-  . = ALIGN(32);
+  . = ALIGN(L1_CACHE_BYTES);
   .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
        *(.data.cacheline_aligned)
   }

Mike
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