[POWERNOW PATCH] x86: powernow-k8 move power management MSRsdeclaration to msr-index.h
From: Jaswinder Singh Rajput
Date: Sat Jun 20 2009 - 06:27:22 EST
Keep all MSRs declaration in msr-index.h to easily access MSRs declaration.
Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@xxxxxxxxx>
---
arch/x86/include/asm/msr-index.h | 9 +++++++++
arch/x86/kernel/cpu/cpufreq/powernow-k8.h | 9 +--------
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4d58d04..103a253 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -109,6 +109,15 @@
#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
#define MSR_AMD64_IBSCTL 0xc001103a
+/* Power Management MSRs */
+#define MSR_FIDVID_CTL 0xc0010041
+#define MSR_FIDVID_STATUS 0xc0010042
+
+#define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* Pstate current limit */
+#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control */
+#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status */
+#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate */
+
/* Fam 10h MSRs */
#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
#define FAM10H_MMIO_CONF_ENABLE (1<<0)
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index 6c6698f..d420ea0 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -73,9 +73,6 @@ struct powernow_k8_data {
/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
/* the register number is placed in ecx, and the data is returned in edx:eax. */
-#define MSR_FIDVID_CTL 0xc0010041
-#define MSR_FIDVID_STATUS 0xc0010042
-
/* Field definitions within the FID VID Low Control MSR : */
#define MSR_C_LO_INIT_FID_VID 0x00010000
#define MSR_C_LO_NEW_VID 0x00003f00
@@ -100,16 +97,12 @@ struct powernow_k8_data {
#define MSR_C_HI_STP_GNT_BENIGN 0x00000001
-/* Hardware Pstate _PSS and MSR definitions */
+/* Hardware Pstate _PSS */
#define USE_HW_PSTATE 0x00000080
#define HW_PSTATE_MASK 0x00000007
#define HW_PSTATE_VALID_MASK 0x80000000
#define HW_PSTATE_MAX_MASK 0x000000f0
#define HW_PSTATE_MAX_SHIFT 4
-#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */
-#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */
-#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */
-#define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* pstate current limit MSR */
/* define the two driver architectures */
#define CPU_OPTERON 0
--
1.6.0.6
--
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