RE: [PATCH] gpio: add Intel Moorestown Platform Langwell chip gpiodriver

[Du, Alek]

David,
>-----Original Message-----
>From: David Brownell [mailto:david-b@xxxxxxxxxxx]
>Sent: 2009年7月2日 7:28
>To: Du, Alek
>Cc: lkml
>Subject: Re: [PATCH] gpio: add Intel Moorestown Platform Langwell chip gpio
>driver
>> Subject: [PATCH] gpio: add Intel Moorestown Platform Langwell chip gpio driver
>>
>> The Langwell chip has a 64-pin gpio block, which is exposed as a PCI device.
>
>Is this a dedicated GPIO-only device?  Or is it like e.g. ICH8
>which shares that device with other functions?

Yes, the GPIO block is just one function of Langwell chip, the Langwell chip is an IOH (IO hub) for the whole system. But the devices on the chip are all exposed as PCI devices.

>
>
>So if LNG is Liquid Natural Gass, then LNW is ... Liquid Natural Water??
>
>Spell it out please.  And use the same name in the driver.name too.

:-), interesting.

>
>You're sure this isn't like a trimmed-down PXA part?
>I think I know some of the history of that register
>model ...  :)

Yeah, I guess it is just like the PXA gpio style, but now the device is PCI style and for i386 arch.

>> +struct lnw_driver_data {
>> +	unsigned	gpio_base;
>> +	unsigned	gpio_nr;
>> +} lnw_driver_datas[] __devinitdata = {
>> +	{ .gpio_base = 0, .gpio_nr = 64 },
>
>Hmm, passing gpio_base here is kind of ugly.
>
>But I guess you're working with platforms that don't
>really have good ways to pass platform-specific data
>through device->platform_data, so you're stuck with
>being ugly...

Yes, for this PCI device, I know it is the only way to pass platform specific data as this.

Thanks for reviewing it. I will submit version 2 according to your comments.

Thanks,
Alek
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